In modern integrated semiconductors, metalized or wiring layers are formed over a semiconductor substrate to interconnect regions of the overall semiconductor device. The metalized layers make conductive contact with underlying layers to establish communication between different semiconductor devices formed on the semiconductor substrate.
As the dimensions of the wiring within the metalized layer are shrinked, the controllability of alignment between the wiring present in an upper layer with a lower underlying layer becomes problematic. Wiring is placed in a metalized layer by forming a pattern of vias and trenches in a dielectric material followed by filling with a conductive material. As the width of the pattern of vias and trenches is reduced, damage to the sidewalls of the vias and trenches due to dry etching and ashing processes employed in their formation leads to unpredictability of the final critical dimension (CD) and resulting alignment difficulties.
Often, a via first trench last (VFTL) scheme is employed to achieve greater accuracy in alignment compared to a trench first via last (TFVL) scheme. In VFTL schemes, the first-formed vias are filled with a sacrifice material that serves as a support for a photomask for patterning trenches. However, such sacrifice materials necessitate removal by chemical agents that introduce further damage to the dielectric materials present.